Semiconductor processing is an intensive activity during which several processes are integrated to achieve a working device. Miniaturization is the process of crowding more semiconductive devices onto a smaller substrate area in order to achieve better device speed, lower energy usage, and better device portability, among others. New processing methods must often be developed to enable miniaturization to be realized. One challenge is to prevent metal or metal silicide agglomeration during back-end-of-line (“BEOL”) processing. The challenge to achieve digit line communication in a memory device that has a low resistivity, is often accompanied by the challenge to achieve a temperature-resistant digit line that is protected from the encroachment of damaging elements during BEOL processing, bum-in testing, and field use.
The advent of the buried digit line (“BDL”) allowed for a lower overall profile of a dynamic random access memory (“DRAM”) device. However, the average grain size (“gs”) of a metallization continues to decrease in a manner that causes grains to form that follow the grain boundaries of a substrate. Accordingly, a higher than desirable resistivity persists despite miniaturization.
Another challenge is to fabricate shallow junctions with shallow source/drain (“S/D”) structures that will receive a contact without entirely destroying the shallow S/D structure. Thus, what is needed is a conductive structure that overcomes some of the challenges of the prior art.